The present invention relates to a semiconductor memory device and a method of testing the same.
In a small-scale memory embedded in a chip, a latch type memory (hereinafter also referred to as a “register file”) using latch circuits as memory elements is used for lower power consumption instead of a common RAM (Random Access Memory). The register file can reduce power consumption by about 70% as compared with the RAM.
FIG. 8 is a block diagram showing a configuration of a conventional register file. As shown in FIG. 8, the conventional register file includes latch type memory cells (LC) M1 to M8, gated clock circuits (GC) 31 to 36, flip-flops (FF) 42, 43, and 45, selectors 53 and 54, and decoders D1 and D2.
The gated clock circuits 31 to 34 are connected to the decoder D1 and the gated clock circuit 35. The gated clock circuit 35 is supplied with a clock signal CK and a write enable signal WEN for allowing data to be written to the latch type memory cells M1 to M8.
The gated clock circuit 36 is supplied with the clock signal CK and a read enable signal REN for allowing data to be read from the latch type memory cells M1 to M8. A data input node of the flip-flop 42 is supplied with a reading address RAD, and a clock input node of the flip-flop 42 is connected to the gated clock circuit 36. The decoder D2 is connected to the flip-flop 42.
Clock input nodes of the flip-flop 43 and the flip-flop 45 are connected to the gated clock circuit 35, and data input nodes of the flip-flop 43 and the flip-flop 45 are supplied with input data Si. Data input nodes of the latch type memory cells M1, M3, M5, and M7 are connected to an output node of the flip-flop 43. Data input nodes of the latch type memory cells M2, M4, M6, and M8 are connected to an output node of the flip-flop 45.
Clock input nodes of the latch type memory cells M1 and M2 are both connected to the gated clock circuit 31; clock input nodes of the latch type memory cells M3 and M4 are both connected to the gated clock circuit 32; clock input nodes of the latch type memory cells M5 and M6 are both connected to the gated clock circuit 33; and clock input nodes of the latch type memory cells M7 and M8 are both connected to the gated clock circuit 34.
An input node of the selector 53 is connected to output nodes of the latch type memory cells M1, M3, M5, and M7, and a select signal input node of the selector 53 is connected to the decoder D2. An input node of the selector 54 is connected to output nodes of the latch type memory cells M2, M4, M6, and M8, and a select signal input node of the selector 54 is connected to the decoder D2. The selector 53 and the selector 54 output output data So.
FIG. 9 is a diagram showing a configuration of the gated clock circuit 35 shown in FIG. 8. It is to be noted that the gated clock circuits 31 to 34 and 36 shown in FIG. 8 have a similar configuration to that of the gated clock circuit 35 shown in FIG. 9.
As shown in FIG. 9, the gated clock circuit 35 includes a latch circuit 57 and an AND circuit 58. The latch circuit 57 is supplied with the write enable signal WEN and an inverted signal of the clock signal CK. The AND circuit 58 is supplied with an output signal of the latch circuit 57 and the clock signal CK. The AND circuit 58 generates and outputs an internal clock signal int.CK.
Specifically, the gated clock circuit 35 as described above outputs the clock signal CK as the internal clock signal int.CK only when the write enable signal WEN is 1 at the time of change of the inputted clock signal CK from 0 to 1. When the write enable signal WEN is 0 at the time of the change, the gated clock circuit 35 does not output a clock waveform and outputs a signal at a zero level.
Operation of the register file shown in FIG. 8 having the above-described configuration will be briefly described in the following. An operation of writing data to the latch type memory cells M1 to M8 will be described first.
At the time of data writing, the write enable signal WEN supplied to the gated clock circuit 35 is activated, whereby an internal clock signal int.CK is generated in response to the externally supplied clock signal CK. The internal clock signal int.CK is supplied to the gated clock circuits 31 to 34 and the flip-flops 43 and 45.
The decoder D1 receives a writing address WAD for specifying a memory cell to be written, and decodes the writing address WAD. The gated clock circuits 31 to 34 selectively activate selecting lines SL1 to SL4 according to a result of the decoding.
On the other hand, the flip-flops 43 and 45 supply an input signal Si supplied thereto to the latch type memory cells M1 to M8 in response to the internal clock signal int.CK supplied thereto. At this time, when the selecting line SL1 is activated, for example, the input signal Si is written to only the latch type memory cells M1 and M2 connected to the selecting line SL1.
An operation of reading data from the latch type memory cells M1 to M8 will be described next. At the time of data reading, the read enable signal REN supplied to the gated clock circuit 36 is activated, whereby an internal clock signal int.CK is generated in response to the externally supplied clock signal CK. The internal clock signal int.CK is supplied to the flip-flop 42.
The decoder D2 receives a reading address RAD for specifying a memory cell to be read via the flip-flop 42, decodes the reading address RAD, and then supplies a result of the decoding to the selectors 53 and 54. The selector 53 is supplied with data retained by the latch type memory cells M1, M3, M5, and M7, and the selector 54 is supplied with data retained by the latch type memory cells M2, M4, M6, and M8. According to the result of the decoding supplied to the selectors 53 and 54, the selectors 53 and 54 selectively output the data as an output signal So.
The register file as described above, however, has a disadvantage of difficulty in conducting a manufacturing test. Specifically, a scan path has come into wide use as a circuit for facilitating a manufacturing test on a chip including a logic circuit, but with the scan path, the manufacturing test is not conducted on latch circuits.
Conventionally, one of the following methods is taken to obviate the above disadvantage. First, there is a method that uses a BIST (Built In Self Test) circuit in wide use for a manufacturing test on a RAM. The method will be described with reference to FIG. 10.
FIG. 10 is a diagram showing a configuration of a chip 1 including a conventional BIST circuit 5 for realizing a manufacturing test on a RAM. As shown in FIG. 10, the chip 1 includes a RAM 3, a test data supply circuit 6, a test data output circuit 7, a test control circuit 8, a control signal input terminal 9, and a test result output terminal 10. The BIST circuit 5 is formed by the test data supply circuit 6, the test data output circuit 7, and the test control circuit 8.
In the BIST circuit 5, in response to a control signal Sci supplied to the test control circuit 8 via the control signal input terminal 9, the test control circuit 8 makes the test data supply circuit 6 internally generate a test signal and supply the test signal to the RAM 3. The test control circuit 8 receives an output signal from the RAM 3 via the test data output circuit 7, and then compares the output signal with an expected value. At this time, when the test control circuit 8 determines that the output signal of the RAM 3 coincides with the expected value, the test control circuit 8 outputs a signal OK indicating that the RAM 3 is normal to the outside via the test result output terminal 10. When the test control circuit 8 determines that the output signal of the RAM 3 does not coincide with the expected value, the test control circuit 8 outputs a signal NG indicating that the RAM 3 is faulty to the outside via the test result output terminal 10.
The chip 1 has a plurality of RAMs 3. The BIST circuit 5 as described above is provided in correspondence with each of the RAMs 3, and has a scale of a few hundred to a few thousand gates for one RAM 3.
Thus, there is a problem in employing the BIST circuit 5 on such a large scale in a register file on a small scale in that circuit area overhead is caused.
Next, there is a method of replacing the latch type memory cells M1 to M8 with scan flip-flops. In the following, functions of scan flip-flops 12 and 14 will be described with reference to FIG. 11. As shown in FIG. 11, the scan flip-flop 12 includes a selector 15 and a flip-flop 17, and the scan flip-flop 14 includes a selector 16 and a flip-flop 18. The scan flip-flop 12 and the scan flip-flop 14 are connected to an input node and an output node, respectively, of a logic circuit 13, for example.
The selectors 15 and 16 are supplied with a selection signal SE. Clock input nodes of the flip-flops 17 and 18 are supplied with a clock signal CK. Also, the selector 15 is supplied with data D and a scan-in signal SI, and the selector 16 is supplied with an output signal of the flip-flop 17 and an output signal of the logic circuit 13.
With the scan flip-flops 12 and 14 as shown in FIG. 11, a scan path that bypasses the logic circuit 13 can be formed by making the selector 15 selectively output the scan-in signal SI and making the selector 16 selectively output the output signal of the flip-flop 17.
By using the scan flip-flops 12 and 14 having the above function in place of the latch type memory cells M1 to M8, a manufacturing test can be conducted with the scan path formed as described above. However, the scan flip-flops 12 and 14 have a circuit area about three times that of the latch type memory cells M1 to M8, thus presenting a problem of an increase in the scale of the circuit as a whole.
In addition, the scan flip-flops 12 and 14 consume about twice as much power as the latch type memory cells M1 to M8. The scan flip-flops 12 and 14, therefore, have another problem in that the reduction in power consumption as compared with RAM is halved.
On the other hand, in conducting a manufacturing test using a scan path, there is another problem of difficulty in testing logic circuits connected to an input side and an output side of a memory. Conventionally, to deal with such a problem, scan flip-flops 12 and 14 are provided between a RAM 3 and logic circuits 13 and 19, respectively, on a chip 20, and wiring that bypasses the RAM 3 is formed from an output node of the scan flip-flop 12, whereby the logic circuits 13 and 19 are tested as shown in FIG. 12, for example.
Specifically, the scan flip-flop 14 is made to selectively output an output signal of the scan flip-flop 12 by a selection signal SE, whereby a scan path that bypasses only the RAM 3 can be formed. It is thus possible to realize a test on the logic circuits 13 and 19 without regard for the effects of the RAM 3.
However, the scan flip-flops 12 and 14 formed on the chip 20 cause problems such as an increase in the circuit scale of the chip 20 as a whole and a decrease in the operating speed of the circuit formed on the chip 20.